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The purpose of this study is to propose a simplifying approach for modelling a reliability test. Modelling the reliability tests of printed circuit board (PCB)/microelectronic component assemblies requires the adoption of several simplifying assumptions. This study introduces and validates simplified assumptions for modeling a four-point bend test on a PCB/wafer-level chip scale packaging assembly.

In this study, simplifying assumptions were used. These involved substituting dynamic imposed displacement loading with an equivalent static loading, replacing the spherical shape of the interconnections with simplified shapes (cylindrical and cubic) and transitioning from a three-dimensional modelling approach to an equivalent two-dimensional model. The validity of these simplifications was confirmed through both quantitative and qualitative comparisons of the numerical results obtained. The maximum principal plastic strain in the solder balls and copper pads served as the criteria for comparison.

The simplified hypotheses were validated through quantitative and qualitative comparisons of the results from various models. Consequently, it was determined that the replacement of dynamic loading with equivalent static loading had no significant impact on the results. Similarly, substituting the spherical shape of interconnections with an equivalent shape and transitioning from a three-dimensional approach to a two-dimensional one did not substantially affect the precision of the obtained results.

This study serves as a valuable resource for researchers seeking to model accelerated reliability tests, particularly in the context of four-point bending tests. The results obtained in this study will assist other researchers in streamlining their numerical models, thereby reducing calculation costs through the utilization of the simplified hypotheses introduced and validated herein.

The aim of this study is to make a contribution towards reducing the deflections of silicon wafers. The deformation of silicon wafers used in the manufacture of electronic micro-components is one of the most common problems encountered by industrialists during manufacturing. Stack warping is typically produced during the process of depositing thin layers on a substrate. This is due to the thermal-mechanical stresses caused by the difference between the thermal expansion coefficients of the materials. Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models.

The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

This paper describes the influence of geometric modification on wafer deformation. The work show also the cruciality of stress reduction in the purpose to obtain less wafer deformation.

This study aims to contribute to the numerical modelling of drop impact on a flip-chip component assembled on printed circuit boards using solder micro-bumps. This contribution is based on the introduction of non-linear fracture mechanics in the numerical approach.

The integration of non-linear fracture mechanics into the numerical approach requires the proposal and validation of several simplifying assumptions. Initially, a dynamic 3D model was simplified to a dynamic 2D model. Subsequently, the dynamic 2D model is replaced with an equivalent static 2D model. The equivalent static 2D model was used to perform calculations considering the non-linear fracture mechanics. A crack was modelled in the critical bump. The J-integral was used as a comparative parameter to study the effects of crack length, crack position and chip thickness on the fracture toughness of the solder bump.

The different simplifying assumptions were validated by comparing the results obtained by the various models. Numerical results showed a high risk of failure at the critical solder bump in a zone close to the intermetallic layer. The obtained results were in agreement with the post-test observations using the “Dye and Pry” methods.

The originality of this study lies in the introduction of non-linear fracture mechanics to model the mechanical response of solder bumps during drop impact. This study led to some interesting conclusions, highlighting the advantage of introducing non-linear fracture mechanics into the numerical simulations of microelectronic components during a drop impact.